1992年-1997年，美国加州大学伯克利分校（UC Berkeley）电子工程，应用物理，博士/PhD
1988年-1989年，美国普度大学 电子工程，电子工程硕士/MSEE
1986年-1988年，美国韦恩州立大学 物理学 理学硕士/MA
1980年-1985年，清华大学，半导体器件与物理，工学学士

2021年-至今，南方科技大学深港微电子学院，产学研教授
2018年-2020年，中国微纳电子国家（重点）实验室 筹备团队负责人
2002年–2017年， 中国 鼎芯集团公司共同创始人、董事长兼CEO
2001年- 2002年， 香港 Authosis Inc风险投资公司高级副总裁兼半导体事业部总裁
1997年- 1999年， 美国 IBM半导体研发中心 顾问级工程师
1989年- 1992年， 美国 国家半导体公司（现德州仪器）仙童研究中心 高级工程师

新原理忆n前沿CMOS器件物理、器件结构与设计、器件建模和工艺集成，包括量子计算4.2K-10mK超低温cryogenic CMOS器件物理和电路设计用建模。

中国信息产业年度新锐人物”
上海市浦东新区“科技领军人物”
专业媒体评选的中国“25位最具影响力的IC人物”
中国半导体行业协会“十年风云人物”创业奖

1.Kai Chen and Chenming Hu, “Performance and Vdd Scaling in Deep Submicrometer CMOS”, IEEE Journal of Solid-State Circuit（JSSC）, vol. 33, no. 10, pp. 1586-1589, October 1998；

2.Kai Chen, J.H. Huang, Jon Duster, Ping Ko and Chenming Hu, A MOSFET Electron Mobility Model of Wide Temperature Range (77K-400K) for IC Simulation, Semiconductor Science and Technology, pp. 355-358, vol. 12, no. 4, April 1997;

3.Kai Chen, G. Zhang, J. Duster, J.H. Huang, Z. Liu, P.K. Ko and C. Hu, MOSFET Inversion Layer Capacitance Model Based on Fermi-Dirac Statistics for Wide Temperature Range, IEEE Journal of Solid-State Electronics (ISSE), pp. 507-509, vol. 40, no. 3, March 1997.

4.Kai Chen, Chenming Hu, and Peng Fang, "Optimizing Quarter and Sub-Quarter Micron CMOS Circuit Speed Considering Interconnect Loading Effect", IEEE Transactions on Electron Devices (T-ED), Vol. 44, No. 9, 1997；

5.Kai Chen, Chenming Hu, Peng Fang, and Ashawant Gupta, "Experimental Confirmation of An Accurate CMOS Gate Delay Model for Gate Oxide and Voltage Scaling", IEEE Electron Device Letters (EDL), Vol. 18, No. 6, pp. 275-277, June 1997；

6.Kai Chen, H. C. Wann, J. Duster, M. Yoshida, P. Ko and C. Hu, "MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold and Gate Voltages", IEEE Journal of Solid-State Electronics (SSE), pp. 1515-1518, Vol. 39, No. 10, October 1996；

7.Kai Chen, C. H. Wann, J. Duster, P. Ko and C. Hu, "The Impact of Device Scaling and Supply Voltage Change on CMOS Gate Performance", IEEE Electron Device Letters (EDL), pp. 202-204, Vol. 17, No. 5, May 1996.

8.Kai Chen, H. C. Wann, J. Duster, P. Pramanik, S. Nariani, P. Ko and C. Hu, "An Accurate Semi-Empirical Saturation Drain Current Model for LDD NMOSFET", IEEE Electron Device Letters (EDL), pp. 145-147, Vol. 17, No. 3, March 1996；

9.Kai Chen, Jian-hui Huang, James Z. Ma, Z.H. Liu, M.C. Jeng, Ping K. Ko and Chenming Hu, "Polysilicon Gate Depletion Effect on IC Performance", IEEE Journal of Solid-State Electronics, pp. 1975-1977, Vol. 38, No. 11, November 1995；

10.Qiuxia Xu and Kai Chen, “Physical Thickness 1.5nm HfZrO Negative Capacitance NMOSFETs”, submitted to IEEE Transactions on Electronics Devices (TED) accepted on 21, 2021;

11.Zhenbiao Li, Wenhai Ni, Jie Ma, Ming Li, Dequn Ma, Dong Zhao, Mehta J., D. Harman, Xianfeng Wang, K.K. O and Kai Chen, “A dual-Band CMOS Transceiver for 3G TD-SCDMA”, Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC), pages 344-607, Feb. 2007;

12.Isabel Yang, Kai Chen and Lisa Su et al, “Sub-60nm Physical Gate Length SOI CMOS”, IEEE Electronics Device Meeting (IEDM) 1999.

13.Jiqing Lu , Wenhui Wang, Jinxuan Liang, Jun Lan , Longyang Lin,Feichi Zhou, Kai Chen, Guobiao Zhang , Mei Shen, and Yida Li "Contact Resistance Reduction of Low Temperature Atomic Layer Deposition ZnO Thin Film Transistor Using Ar Plasma Surface Treatment," in IEEE Electron Device Letters, vol. 43, no. 6, pp. 890-893, June 2022,doi:10.1109/LED.2022.3169345.

14.Muhammad Zaheer , Aziz-Ur-Rahim Bacha, Iqra Nabi , Jun Lan, Wenhui Wang, Mei Shen, Kai Chen et al, “All Solution-Processed Inorganic, Multilevel Memristors Utilizing Liquid Metals Electrodes Suitable for Analog Computing”，ACS Omega, 22/9/2022.

15. Guobiao Zhang, Hongyu Yu, Shenming Zhou and Kai Chen, “Methods for Making Three-Dimensional Module”. United States Patent and Trademark Office, CONFIRMATION NO.4882 FILING RECEIPT Date Mailed:12/20/2021.